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document number: mc33982 rev. 12.0, 1/2007 freescale semiconductor advance information * this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, in c., 2007. all rights reserved. single intelligent high-current self-protected silicon high-side switch (2.0 m ? ) the 33982B is a self-protected silicon 2.0 m ? high-side switch used to replace electromechanical relays, fuses, and discrete devices in power management applications. the 33982B is designed for harsh environments, and it includes self-re covery features. the device is suitable for loads with high inrush current, as well as motors and all types of resistive and inductive loads. programming, control, and diagnostics are implemented via the serial peripheral interface (spi). a dedicated parallel input is available for alternate and pulse width modulation (pwm) control of the output. spi programmable fault trip thresholds allow the device to be adjusted for optimal performance in the application. the 33982B is packaged in a power-enhanced 12 x 12 nonleaded pqfn package with exposed tabs. features ? single 2.0 m ? max high-side switch with parallel input or spi control ? 6.0 v to 27 v operating voltage with standby currents < 5.0 a ? output current monitoring with two spi-selectable current ratios ? spi control of overcurrent limit, overcurrent fault blanking time, output-off open load detection, output on/off control, watchdog time-out, slew rates, and fault status reporting ? spi status reporting of overcurrent, open and shor ted loads, overtemperature shutdown, undervoltage and overvoltage shutdown, fail-safe pin status, and program status ? enhanced -16 v reverse polarity v pwr protection figure 1. 33982B simplified application diagram high-side switch 33982B ordering information device temperature range (t a ) package mc33982Bpna/r2 -40 c to 125 c 16 pqfn scale 1:1 bottom view pna suffix 98arl10521d 16-pin pqfn vdd i/o i/o so sclk cs si i/o i/o a/d vpwr fs wake si sclk cs so rst in csns fsi gnd hs gnd load 33982B mcu v dd v dd v dd v pwr gnd pwr gnd
analog integrated circuit device data 2 freescale semiconductor 33982 internal block diagram internal block diagram figure 2. 33982B simplified internal block diagram gnd programmable watchdog 310 ms?2500 ms overtemperature detection selectable output current recopy 1/5400 or 1/40000 open load detection logic spi 3.0 mhz selectable over- current low detection 0.15 ms?155 ms selectable low detection 15 a?50 a selectable overcurrent high detection 150 a or 100 a internal regulator programmable switch delay 0 ms?525 ms selectable slew rate gate drive overvoltage protection hs csns vpwr vdd cs so si sclk fs in rst wake fsi v ic v ic i dwn r dwn i up i up blanking time overcurrent
analog integrated circuit device data freescale semiconductor 3 33982 pin connections pin connections figure 3. 33982B pin connections table 1. pin definitions functional descriptions of many of these pins can be fo und in the functional pin description section beginning on page 15 . pin number pin name pin function formal name definition 1 csns output output current monitoring this pin is used to output a current proportional to the high-side output current and used externally to generate a ground-referenced voltage for the microcontroller to monitor output current. 2 wake input wake this pin is used to input a logic [1] signal in order to enable the watchdog timer function. 3rst input reset (active low) this input pin is used to initiali ze the device configuration and fault registers, as well as place the device in a low current sleep mode. 4 in input direct input the input pin is used to directly control the output. 5fs output fault status (active low) this is an open drain configured out put requiring an external pullup resistor to v dd for fault reporting. 6 fsi input fail-safe input the value of the resistance connected between this pin and ground determines the state of the output after a watchdog time-out occurs. 7cs input chip select (active low) this input pin is connected to a chip select output of a master microcontroller (mcu). 8 sclk input serial clock this input pin is connected to the mcu providing the required bit shift clock for spi communication. 9 si input serial input this is a command data input pin connected to the spi serial data output of the mcu or to the so pin of the previous devic e in a daisy chain of devices. 10 vdd input digital drain voltage (power) this is an external voltage input pi n used to supply power to the spi circuit. hs hs 16 15 vpwr 14 gnd 13 csns in fs fsi cs sclk rst wake si vdd so nc 1 11 10 9 8 7 6 5 4 3 2 12 transparent top view
analog integrated circuit device data 4 freescale semiconductor 33982 pin connections 11 so output serial output this output pin is connected to the spi serial data input pin of the mcu or to the si pin of the next dev ice in a daisy c hain of devices. 12 nc nc no connect this pin may not be connected. 13 gnd ground ground this pin is the ground for the logic and analog circuitry of the device. 14 vpwr input positive power supply this pin connects to the positive power supply and is the source input of operational power for the device. 15, 16 hs output high-side output protected high-side power output to the load. output pins must be connected in parallel for operation. table 1. pin definitions (continued) functional descriptions of many of these pins can be fo und in the functional pin description section beginning on page 15 . pin number pin name pin function formal name definition
analog integrated circuit device data freescale semiconductor 5 33982 electrical characteristics maximum ratings electrical characteristics maximum ratings table 2. maximum ratings all voltages are with respect to ground unless otherwise noted. rating symbol value unit electrical ratings operating voltage range steady-state v pwr -16 to 41 v v dd supply voltage v dd -0.3 to 5.5 v input/output voltage (1) v in , rst , fsi, csns, si, sclk, cs , fs - 0.3 to 7.0 v so output voltage (1) v so - 0.3 to v dd + 0.3 v wake input clamp current i cl(wake) 2.5 ma csns input clamp current i cl(csns) 10 ma output current (2) i hs 60 a output voltage positive negative v hs 41 -15 v output clamp energy (3) e cl 1.5 j esd voltage (4) human body model (hbm) charge device model (cdm) corner pins (1, 12, 15, 16) all other pins (2, 11, 13, 14) v esd1 v esd3 2000 750 500 v
analog integrated circuit device data 6 freescale semiconductor 33982 electrical characteristics maximum ratings thermal ratings operating temperature ambient junction t a t j - 40 to 125 - 40 to 150 c storage temperature t stg - 55 to 150 c thermal resistance (5) junction-to-case junction-to-ambient r jc r ja <1.0 20 c/w peak package reflow temperature during reflow (6) , (7) t pprt note 7 c notes 1. exceeding this voltage limit may cause permanent damage to the device. 2. continuous high-side output current rating so long as maximum junction temperature is not exceeded. calculation of maximum ou tput current using package thermal resistance is required. 3. active clamp energy using single-pulse method (l = 16 mh, r l = 0, v pwr = 12 v, t j = 150c). 4. esd1 testing is performed in accordance with the human body model (hbm) (c zap = 100 pf, r zap = 1500 ?); esd3 testing is performed in accordance with the charge device model (cdm), robotic (czap = 4.0 pf). 5. device mounted on a 2s2p test board per jedec jesd51-2. 6. pin soldering temperature limit is for 10 seconds maximum duration. not designed for immersion soldering. exceeding these lim its may cause malfunction or permanent damage to the device. 7. freescale?s package reflow capability meets pb-free requir ements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core id to view all orderable parts . (i.e. mc33xxxd enter 33xxx), and review parametrics. table 2. maximum ratings all voltages are with respect to ground unless otherwise noted. rating symbol value unit
analog integrated circuit device data freescale semiconductor 7 33982 electrical characteristics static electrical characteristics static electrical characteristics table 3. static electr ical characteristics characteristics noted under conditions 4.5 v v dd 5.5 v, 6.0 v v pwr 27 v, -40 c t a 125 c unless otherwise noted. typical values noted reflect th e approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit power input battery supply voltage range full operational v pwr 6.0 ? 27 v v pwr operating supply current output on, i hs = 0 a i pwr(on) ??20 ma vpwr supply current output off, open load detection disabled, wake > 0.7 v dd , rst = v logic high i pwr(sby) ??5.0 ma sleep state supply current (v pwr < 14 v, rst < 0.5 v, wake < 0.5 v) t j = 25 c t j = 85 c i pwr(sleep) ? ? ? ? 10 50 a vdd supply voltage v dd(on) 4.5 5.0 5.5 v vdd supply current no spi communication 3.0 mhz spi communication i dd(on) ? ? ? ? 1.0 5.0 ma vdd sleep state current i dd(sleep) ??5.0 a overvoltage shutdown threshold v pwr(ov) 28 32 36 v overvoltage shutdown hysteresis v pwr(ovhys) 0.2 0.8 1.5 v undervoltage output shutdown threshold (8) v pwr(uv) 5.0 5.5 6.0 v undervoltage hysteresis (9) v pwr(uvhys) ?0.25?v undervoltage power-on reset v pwr(uvpor) ??5.0v power output output drain-to-source on resistance ( i hs = 30 a, t j = 25 c) v pwr = 6.0 v v pwr = 10 v v pwr = 13 v r ds(on) ? ? ? ? ? ? 3.0 2.0 2.0 m ? output drain-to-source on resistance (i hs = 30 a, t j = 150 c) v pwr = 6.0 v v pwr = 10 v v pwr = 13 v r ds(on) ? ? ? ? ? ? 5.1 3.4 3.4 m ? output source-to-drain on resistance (i hs = 30 a, t j = 25 c) (10) v pwr = -12 v r ds(on) ?2.04.0 m ? notes 8. this applies to all internal dev ice logic that is supplied by v pwr and assumes that the external v dd supply is within specification. 9. this applies when the undervoltage fault is not latched (in = 0). 10. source-drain on resistance (reverse drain-to -source on resistance) with negative polarity v pwr .
analog integrated circuit device data 8 freescale semiconductor 33982 electrical characteristics static electrical characteristics power output (continued) output overcurrent high detection levels (9.0 v < v pwr < 16 v) soch = 0 soch = 1 i och0 i och1 120 80 150 100 180 120 a overcurrent low detection levels (socl[2:0]) 000 001 010 011 100 101 110 111 i ocl0 i ocl1 i ocl2 i ocl3 i ocl4 i ocl5 i ocl6 i ocl7 41 36 32 29 25 20 16 12 50 45 40 35 30 25 20 15 59 54 48 41 35 30 24 18 a current sense ratio (9.0 v < v pwr < 16 v, csns < 4.5 v) dicr d2 = 0 dicr d2 = 1 c sr0 c sr1 ? ? 1/5400 1/40000 ? ? ? current sense ratio (c sr0 ) accuracy output current 10 a 20 a 25 a 30 a 40 a 50 a c sr0_acc - 20 -14 -13 -12 -13 -13 ? ? ? ? ? ? 20 14 13 12 13 13 % current sense ratio (c sr1 ) accuracy output current 10 a 20 a 25 a 30 a 40 a 50 a c sr1_acc - 25 -19 -18 -17 -18 -18 ? ? ? ? ? ? 25 19 18 17 18 18 % current sense clamp voltage csns open, i hs = 59.0 a v cl(csns) 4.5 6.0 7.0 v open load detection current (11) i oldc 30 ? 100 a output fault detection threshold output programmed off v old(thres) 2.0 3.0 4.0 v notes 11. output off open load detection current is the current requir ed to flow through the load for the purpose of detecting the exi stence of an open load condition when the spec ific output is commanded off. table 3. static electrical characteristics (continued) characteristics noted under conditions 4.5 v v dd 5.5 v, 6.0 v v pwr 27 v, -40 c t a 125 c unless otherwise noted. typical values noted reflect th e approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 9 33982 electrical characteristics static electrical characteristics power output (continued) output negative clamp voltage 0.5 a < i hs < 2.0 a, output off v cl - 20 ? -15 v overtemperature shutdown (12) t sd 160 175 190 c overtemperature shutdown hysteresis (12) t sd(hys) 5.0 ? 20 c control interface input logic high voltage (13) v ih 0.7 v dd ? ? v input logic low voltage (13) v il ? ? 0.2 v dd v input logic voltage hysteresis (14) v in(hys) 100 600 1200 mv input logic pulldown current (sclk, in, si) i dwn 5.0 ? 20 a rst input voltage range v rst 4.5 5.0 5.5 v so, fs tri-state capacitance (15) c so ? ? 20 pf input logic pulldown resistor (rst ) and wake r dwn 100 200 400 k ? input capacitance (15) c in ? 4.0 12 pf wake input clamp voltage (16) i cl(wake) < 2.5 ma v cl(wake) 7.0 ? 14 v wake input forward voltage i cl(wake) = -2.5 ma v f(wake) - 2.0 ? -0.3 v so high-state output voltage i oh = 1.0 ma v soh 0.8 v dd ? ? v fs , so low-state output voltage i ol = -1.6 ma v sol ? 0.2 0.4 v so tri-state leakage current cs > 0.7 v dd i so(leak) -5.0 0.0 5.0 a input logic pullup current (17) cs , v in > 0.7 v dd i up 5.0 ? 20 a fsi input pin external pulldown resistance fsi disabled, hs indeterminate fsi enabled, hs off fsi enabled, hs on rfs rfsdis rfsoff rfson ? 6.0 30 0.0 10 ? 1.0 14 ? k ? notes 12. guaranteed by process monitoring. not production tested. 13. upper and lower logic threshold voltage range applies to si, cs , sclk, rst , in, and wake input signals. the wake and rst signals may be supplied by a derived voltage reference to v pwr . 14. no hysteresis on fsi and wake pins. parameter is guaran teed by process monitoring but is not production tested. 15. input capacitance of si, cs , sclk, rst , and wake. this parameter is guaranteed by process monitoring but is not production tested. 16. the current must be limited by a series resistance when using voltages > 7.0 v. 17. pullup current is with cs open. cs has an active internal pullup to v dd . table 3. static electrical characteristics (continued) characteristics noted under conditions 4.5 v v dd 5.5 v, 6.0 v v pwr 27 v, -40 c t a 125 c unless otherwise noted. typical values noted reflect th e approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 10 freescale semiconductor 33982 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 4. dynamic electr ical characteristics characteristics noted under conditions 4.5 v v dd 5.5 v, 6.0 v v pwr 27 v, -40 c t a 150 c unless otherwise noted. typical values noted reflect th e approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit power output timing output rising slow slew rate a (dicr d3 = 0) (18) 9.0 v < v pwr < 16 v sr ra_slow 0.2 0.6 1.2 v/ s output rising slow slew rate b (dicr d3 = 0) (19) 9.0 v < v pwr < 16 v sr rb_slow 0.03 0.1 0.3 v/ s output rising fast slew rate a (dicr d3 = 1) (18) 9.0 v < v pwr < 16 v sr ra_fast 0.4 1.0 4.0 v/ s output rising fast slew rate b (dicr d3 = 1) (19) 9.0 v < v pwr < 16 v sr rb_fast 0.03 0.1 1.2 v/ s output falling slow slew rate a (dicr d3 = 0) (18) 9.0 v < v pwr < 16 v sr fa_slow 0.2 0.6 1.2 v/ s output falling slow slew rate b (dicr d3 = 0) (19) 9.0 v < v pwr < 16 v sr fb_slow 0.03 0.1 0.3 v/ s output falling fast slew rate a (dicr d3 = 1) (18) 9.0 v < v pwr < 16 v sr fa_fast 0.8 2.0 4.0 v/ s output falling fast slew rate b (dicr d3 = 1) (19) 9.0 v < v pwr < 16 v sr fb_fast 0.1 0.35 1.2 v/ s output turn-on delay time in fast/slow slew rate (20) dicr = 0, dicr = 1 t dly(on) 1.0 18 100 s output turn-off delay time in slow slew rate mode (21) dicr = 0 t dly_slow(off) 20 230 500 s output turn-off delay time in fast slew rate mode (21) dicr = 1 t dly_fast(off) 10 60 200 s direct input switching frequency (dicr d3 = 0) f pwm ? 300 ? hz notes 18. rise and fall slew rates a measured across a 5.0 ? resistive load at high-side output = 0.5 v to v pwr - 3.5 v. these parameters are guaranteed by process monitoring. 19. rise and fall slow slew rates b measured across a 5.0 ? resistive load at high-side output = v pwr - 3.5 v to v pwr - 0.5 v. these parameters are guaranteed by process monitoring . 20. turn-on delay time measured from rising edge of any signal (in, sclk, cs ) that would turn the output on to v hs = 0.5 v with r l = 5.0 ? resistive load. 21. turn-off delay time measured from fa lling edge of any signal (in, sclk, cs ) that would turn the output off to v hs = v pwr - 0.5 v with r l = 5.0 ? resistive load.
analog integrated circuit device data freescale semiconductor 11 33982 electrical characteristics dynamic electrical characteristics power output timing (continued) overcurrent low detection blanking time (oclt [1:0]) 00 01 10 11 t ocl0 t ocl1 t ocl2 t ocl3 108 7.0 0.8 0.08 155 10 1.2 0.15 202 13 1.6 0.25 ms overcurrent high detection blanking time t och 1.0 10 20 s cs to csns valid time (22) t cnsval ? ? 10 s output switching delay time (osd [2:0]) 000 001 010 011 100 101 110 111 t osd0 t osd1 t osd2 t osd3 t osd4 t osd5 t osd6 t osd7 ? 52 105 157 210 262 315 367 0 . 0 75 150 225 300 375 450 525 ? 95 195 293 390 488 585 683 ms watchdog time-out (wd [1:0]) (23) 00 01 10 11 t wdto0 t wdto1 t wdto2 t wdto3 434 207 1750 875 620 310 2500 1250 806 403 3250 1625 ms spi interface characteristics recommended frequency of spi operation f spi ? ? 3.0 mhz required low state duration for rst (24) t wrst ? 50 167 ns notes 22. time necessary for the csns to be within 5% of the targeted value. 23. watchdog time-out delay measured fr om the rising edge of wake to rst from a sleep state condition to output turn-on with the output driven off and fsi floating. the values shown ar e for wdr setting of [00]. the accuracy of t wdto is consistent for all configured watchdog timeouts. 24. rst low duration measured with outputs enabled and going to off or disabled condition. table 4. dynamic electrical characteristics (continued) characteristics noted under conditions 4.5 v v dd 5.5 v, 6.0 v v pwr 27 v, -40 c t a 150 c unless otherwise noted. typical values noted reflect th e approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 12 freescale semiconductor 33982 electrical characteristics dynamic electrical characteristics spi interface characteristics rising edge of cs to falling edge of cs (required setup time) (25) t cs ? ? 300 ns rising edge of rst to falling edge of cs (required setup time) (25) t enbl ? ? 5.0 s falling edge of cs to rising edge of sclk (required setup time) (25) t lead ? 50 167 ns required high state duration of sclk (required setup time) (25) t wsclkh ? ? 167 ns required low state duration of sclk (required setup time) (25) t wsclkl ? ? 167 ns falling edge of sclk to rising edge of cs (required setup time) (25) t lag ? 50 167 ns si to falling edge of sclk (required setup time) (26) t si(su) ? 25 83 ns falling edge of sclk to si (required setup time) (26) t si(hold) ? 25 83 ns so rise time c l = 200 pf t rso ? 25 50 ns so fall time c l = 200 pf t fso ? 25 50 ns si, cs , sclk, incoming signal rise time (26) t rsi ? ? 50 ns si, cs , sclk, incoming signal fall time (26) t fsi ? ? 50 ns time from falling edge of cs to so low impedance (27) t so(en) ? ? 145 ns time from rising edge of cs to so high impedance (28) t so(dis) ? 65 145 ns time from rising edge of sclk to so data valid (29) 0.2 v dd so 0.8 v dd , c l = 200 pf t valid ? 65 105 ns notes 25. maximum setup time required for the 33982B is the minimum guaranteed time needed from the microcontroller. 26. rise and fall time of incoming si, cs , and sclk signals suggested for de sign consideration to prevent the occurrence of double pulsing. 27. time required for output status data to be available for use at so. 1.0 k ? on pullup on cs . 28. time required for output status data to be terminated at so. 1.0 k ? on pullup on cs . 29. time required to obtain valid data out from so following the rise of sclk. table 4. dynamic electrical characteristics (continued) characteristics noted under conditions 4.5 v v dd 5.5 v, 6.0 v v pwr 27 v, -40 c t a 150 c unless otherwise noted. typical values noted reflect th e approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 13 33982 electrical characteristics timing diagrams timing diagrams figure 4. output slew rate and time delays figure 5. overcurrent shutdown figure 6. overcurrent low and high detection vpwr vpwr - 0.5v vpwr - 3v 0.5v tdly ( off) srra srrb srfa srfb cs tdly (on) v pwr v pwr -0.5 v v pwr -3.5 v 0.5 v t dly(on) sr rb_slow & sr fb_slow & sr fb_fast sr fa_slow & sr fa_fast sr ra_slow & hs sr ra _fast sr rb_fast t dly_slow(off) & t dly_fast(off) i oclx i och x t oclx t och time load current i och 0 t ocl0 t ocl1 t ocl2 t ocl3 t och x time load current i och1 i ocl0 i ocl2 i ocl3 i ocl4 i ocl5 i ocl6 i ocl7 i ocl1
analog integrated circuit device data 14 freescale semiconductor 33982 electrical characteristics figure 6 illustrates the overcurrent detection level (i oclx , i ochx ) the device can reach for each overcur - rent detection blanking time ( t ochx , t oclx ): ? during t ochx , the device can reach up to ioch0 overcurrent level. ? during t ocl3 or t ocl2 or t ocl1 or t ocl0 , the device can be programmed to detect up to iocl0. figure 7. input timing switching characteristics figure 8. sclk waveform and valid so data delay time si rstb csb sclk don?t care don?t care don?t care valid valid vih vil vih vih vih vil vil vil twrstb tlead twsclkh trsi tlag tsisu twsclkl tsi(hold) tfsi 0.7 vdd 0.2 vdd 0.7vdd 0.2vdd 0.2vdd 0.7vdd 0.7vdd tcsb tenbl rst sclk si cs 0.2 v dd t wrst t enbl 0.2 v dd t lead t wsclkh t rsi 0.7 v dd 0.2 v dd 0.7 v dd 0.2 v dd t si(su) t wsclkl t si(hold) t fsi 0.7 v dd t cs t lag v ih v ih v il v il v ih v il v ih v ih so so sclk voh vol voh vol voh vol tfsi tdlylh tdlyhl t valid trso tfso 3.5v 50% trsi high-to-low 1.0v 0.7 vdd 0.2vdd 0.2 vdd 0.7 vdd low-to-high t rsi t fsi 0.7 v dd sclk so so v oh v ol v oh v ol v oh v ol 1.0 v 0.2 v dd 0.7 v dd t rso t fso 0.2 v dd t so(en) t so(dis) 3.5 v low to high high to low t valid
analog integrated circuit device data freescale semiconductor 15 33982 functional description introduction functional description introduction the 33982B is a self-protected silicon 2.0 m ? high-side switch used to replace electromechanical relays, fuses, and discrete devices in power management applications. the 33982B is designed for harsh environments, including self- recovery features. the device is suitable for loads with high inrush current, as well as motors and all types of resistive and inductive loads. programming, control, and diagnostics are implemented via the serial peripheral interface (spi). a dedicated parallel input is available for alternate and pulse width modulation (pwm) control of the output. spi programmable fault trip thresholds allow the device to be adjusted for optimal performance in the application. the 33982B is packaged in a power-enhanced 12 x 12 nonleaded pqfn package with exposed tabs. functional pin description output current monitoring (csns) the csns pin outputs a current proportional to the high- side output current and used exte rnally to generate a ground- referenced voltage for the microcontroller to monitor output current. wake (wake) this pin is used to input a logic [1] signal in order to enable the watchdog timer function. an internal clamp protects this pin from high damaging volt ages when the output is current limited with an external resi stor. this input has a passive internal pulldown. reset (rst ) this input pin is used to initialize the device configuration and fault registers, as well as place the device in a low current sleep mode. the pin also starts the watchdog timer when transitioning from logic low to logic high. this pin should not be allowed to be logic high until v dd is in regulation. this pin has a passive internal pulldown. direct in (in) the input pin is used to directly control the output. this input has an active internal pulldown current source and requires cmos logic levels. this input may be configured via spi. fault status (fs ) this is an open drain c onfigured output requiring an external pullup resistor to v dd for fault reporting. when a device fault condition is detect ed, this pin is active low. specific device diagnostic faults are reported via the spi so pin. fail-safe input (fsi) the value of the resistance connected between this pin and ground determines the state of the output after a watchdog time-out occurs. depending on the resistance value, either the output is off or on. when the fsi pin is connected to gnd, the watchdog circuit and fail-safe operation are disabled. this pin incorporates an active internal pullup current source. chip select (cs ) this input pin is connected to a chip select output of a master microcontroller (mcu). the mcu determines which device is addressed (selected) to receive data by pulling the cs pin of the selected device logic low, enabling spi communication with the device. other unselected devices on the serial link having their cs pins pulled up logic high disregard the spi communication data sent. this pin incorporates an active internal pullup current source. serial clock (sclk) this input pin is connected to the mcu providing the required bit shift clock for spi communication. it transitions one time per bit transferred at an operating frequency, f spi , defined by the communication interface. the 50 percent duty cycle cmos-level serial cloc k signal is idle between command transfers. the signal is used to shift data into and out of the device. this input has an active internal pulldown current source. serial interface (si) this is a command data input pin connected to the spi serial data output of the mcu or to the so pin of the previous device in a daisy chain of devices. the input requires cmos logic level signals and incorporates an active internal pulldown current source. device control is facilitated by the input's receiving the msb first of a serial 8-bit control command. the mcu ensures data is available upon the falling edge of sclk. the logic state of si present upon the rising edge of sclk loads that bit command into the internal command shift register. digital drain voltage power (vdd) this is an external voltage input pin used to supply power to the spi circuit. in the event v dd is lost, an internal supply provides power to a portion of the logic, ensuring limited functionality of the device. all device configuration registers are reset.
analog integrated circuit device data 16 freescale semiconductor 33982 functional description functional pin description serial output (so) this output pin is connected to the spi serial data input pin of the mcu or to the si pin of the next device in a daisy chain of devices. this output will remain tri-stated (high impedance off condition) so long as the cs pin of the device is logic high. so is only active when the cs pin of the device is asserted logic low. the generated so output signals are cmos logic levels. so output data is available on the falling edge of sclk and transitions immediately on the rising edge of sclk. positive power supply (vpwr) this pin connects to the positive power supply and is the source input of operational power for the device. the vpwr pin is a backside surface mount tab of the package. high-side output (hs) this pin protects high-side power output to the load. output pins must be connected in parallel for operation.
analog integrated circuit device data freescale semiconductor 17 33982 functional device operation operational modes functional device operation operational modes the 33982B has four operat ing modes: sleep, normal, fault, and fail-safe. table 5 summarizes details contained in succeeding paragraphs. sleep mode the default mode of the 33982B is the sleep mode. this is the state of the device after first applying battery voltage (v pwr ), prior to any i/o transitions. this is also the state of the device when the wake and rst are both logic [0]. in the sleep mode, the output and all unused internal circuitry, such as the internal 5.0 v regulator, are off to minimize current draw. in addition, all spi-config urable features of the device are as if set to logic [0]. the device will transition to the normal or fail-safe operati ng modes based on the wake and rst inputs as defined in table 5 . normal mode the 33982B is in normal mode when: ?v pwr is within the normal voltage range. ? rst pin is logic [1]. ? no fault has occurred. fail-safe mode and watchdog if the fsi input is not grounded, the watchdog time-out detection is active when either the wake or rst input pin transitions from logic [0] to logic [1]. the wake input is capable of being pulled up to v pwr with a series of limiting resistance that limits the internal clamp current. the watchdog time-out is a multiple of an internal oscillator and is specified in table 14 . as long as the wd bit (d7) of an incoming spi message is toggled within the minimum watchdog time-out period (wdto), based on the programmed value of the wdr the device will operate normally. if an internal watchdog time-out occurs before the wd bit, the device will revert to a fail-safe mode until the device is reinitialized. during the fail-safe mode, the output will be on or off depending upon the resistor rfs connected to the fsi pin, regardless of the state of the va rious direct inputs and modes ( table 6 ). in this mode, the spi r egister content is retained except for overcurrent high and low detection levels and timing, which are reset to their default value (socl, soch, oclt). the watchdog, overvo ltage, overte mperature, and overcurrent circuitry (with defaul t value for this one) are fully operational. the fail-safe mode can be detected by monitoring the wdto bit d2 of the wdr register. this bit is logic [1] when the device is in fail-safe mode. the device can be brought out of the fail-safe mode by transitioning the wake and rst pins from logic [1] to logic [0] or forcing the fsi pin to logic [0]. table 5 summarizes the various methods for resetting the device from the latched fail-safe mode. if the fsi pin is tied to gnd, the watchdog fail-safe operation is disabled. loss of v dd if the external 5.0 v supply is not within specification, or even disconnected, all register content is reset. the output can still be driven by the direct input in. the 33982B uses the battery input to power the output mosfet-related current sense circuitry and any other internal logic, providing fail- safe device operation with no v dd supplied. in this state, the watchdog, overvoltage, overte mperature, and overcurrent circuitry are fully operational with default values. current recopy is active with the default current recopy value. table 5. fail-saf e operation and transitions to other 33982B modes mode fs wake rst wdto comments sleep x 0 0 x device is in sleep mode. all outputs are off. normal 1 x 1 no normal mode. watchdog is active if enabled. fault 0 1 x no the device is currently in fault mode. the faulted output is off. 0 x 1 fail- safe 1 0 1 yes watchdog has timed out and the device is in fail- safe mode. the output is as configured with the rfs resistor connected to fsi. rst and wake must be transitioned to logic [0] simultaneously to bring the device out of the fail-safe mode or momentarily tied the fsi pin to ground. 1 1 1 1 0 1 1 1 0 x = don?t care. table 6. output stat e during fail-safe mode rfs (k ? ) high-side state 0 fail-safe mode disabled 10 hs off 30 hs on
analog integrated circuit device data 18 freescale semiconductor 33982 functional device operation protection and diagnosis features fault mode the 33982B indicates the followin g faults as they occur by driving the fs pin to logic [0]: ? overtemperature fault ? overvoltage and undervoltage fault ? open load fault ? overcurrent fault (high and low) the fs pin will automatically return to logic [1] when the fault condition is removed, e xcept for overcurrent and in some cases undervoltage. fault information is retained in the fault register and is available (and reset) via the so pin during the first valid spi communication (refer to table 16 ). protection and diagnosis features overtemperature fault (non-latching) the 33982B incorporates over temperature detection and shutdown circuitry in the output structure. overtemperature detection is enabled when the ou tput is in the on state. for the output, an overtemperature fault (otf) condition results in the faulted output tu rning off until the temperature falls below the t sd(hys) . this cycle will cont inue indefinitely until action is taken by the mcu to shut off the output, or until the offending load is removed. when experiencing this fault, the otf fault bit will be set in the status register and cleare d after either a valid spi read or a power reset of the device. overvoltage fault (non-latching) the 33982B shuts down the out put during an overvoltage fault (ovf) condition on the v pwr pin. the output remains in the off state until the overvo ltage condition is removed. when experiencing this fault, th e ovf fault bit is set in bit od1 and cleared after either a valid spi read or a power reset of the device. the overvoltage protection and diagnostic can be disabled through spi (bit ov_dis). undervoltage shutdown (latching or non-latching) the output(s) will latch off at some battery voltage below 6.0 v. as long as the v dd level stays within the normal specified range, the internal l ogic states within the device will be sustained. in the case where battery voltage drops below the undervoltage threshold (vpwruv) output will turn off, fs will go to logic [0], and the fault register uvf bit will be set to 1. two cases need to be considered when the battery level recovers: ? if output(s) command is (are) low, fs will go to logic [1] but the uvf bit will remain set to 1 until the next read operation. ? if the output command is on, then fs will remain at logic [0]. the output must be turned off and on again to re-enable the state of output and release fs . the uvf bit will remain set to 1 until the next read operation. the undervoltage protection can be disabled through spi (bit uv_dis = 1). in this case, the fs and uvf bit do not report any undervoltage fault condition and the output state will not be changed as long as the batt ery voltage does not drop any lower than 2.5 v. open load fault (non-latching) the 33982B incorporates open load detection circuitry on the output. output open load fault (olf) is detected and reported as a fault conditi on when the output is disabled (off). the open load fault is detected and latched into the status register after the internal gate voltage is pulled low enough to turn off the output. the olf fault bit is set in the status register. if the open load fault is removed, the status register will be cleared after reading the register. the open load protection can be disabled through spi (bit ol_dis). it is recommended to disable the open load detection circuitry (ol_dis bit sets to logic [1]) in case of a permanent open load fault condition. overcurrent fault (latching) the 33982B has eight programmable overcurrent low detection levels (i ocl ) and two programmable overcurrent high detection levels (i och ) for maximum device protection. the two selectable, simultaneously active overcurrent detection levels, defined by i och and i ocl , are illustrated in figure 6 . the eight different overcurrent low detection levels (i ocl0 : i ocl7 ) are likewise illustrated in figure 6 . if the load current level ever reaches the selected overcurrent low detection leve l and the overcurrent condition exceeds the programmed overcurrent time period (t oc x ), the device will latch the output off. if at any time the curr ent reaches the selected i och level, then the device will immediately latch the fault and turn off the output, regardless of the selected t ocl driver. for both cases, the device output will stay off indefinitely until the device is commanded off and then on again.
analog integrated circuit device data freescale semiconductor 19 33982 functional device operation protection and diagnosis features reverse battery the output survives the applic ation of reverse voltage as low as -16 v. under these cond itions, the output?s gate is enhanced to keep the junction temperature less than 150c. the on resistance of the output is fairly similar to that in the normal mode. no additional passive components are required. ground disconnect protection in the event the 33982B ground is disconnected from load ground, the device protects itself and safely turns off the output regardless the state of the output at the time of disconnection. a 10 k resistor needs to be added between the wake pin and the rest of the circuitry in order to ensure that the device turns off in case of ground disconnect and to prevent this pin to exce ed its maximum ratings. table 7. device behavior in case of undervoltage spss (vpwr batter voltage) ?? state uv enable in=0 (falling vpwr) uv enable in=0 (rising vpwr) uv enable in=1 (falling vpwr) uv enable in=1 (rising vpwr) uv disable in=x (falling or rising vpwr) vpwr > vpwruv output state off off on off off fs state 1 1 1 0 1 spi fault register uvf bit 0 1 until next read 0 1 0 vpwruv > vpwr > uvpor output state off off off off off fs state 0 0 0 0 1 spi fault register uvf bit 1 1 until next read 1 1 0 uvpor > vpwr > 2.5 v ? output state off off off off off fs state 1 1 1 1 1 spi fault register uvf bit 1 until next read 1 until next read 1 until next read 1 until next read 0 2.5 v > vpwr > 0v output state off off off off off fs state 1 1 1 1 1 spi fault register uvf bit 1 until next read 1 until next read 1 until next read 1 until next read 0 comments uv fault is not latched uv fault is not latched uv fault is latched ? typical value; not guaranteed ?? while vdd remains within specified range.
analog integrated circuit device data 20 freescale semiconductor 33982 functional device operation logic commands and registers functional device operation logic commands and registers spi protocol description the spi interface has a full duplex, three-wire synchronous data transfer with four i /o lines associated with it: serial clock (sclk), serial input (si), serial output (so), and chip select ( cs ). the si / so pins of the 33982B follow a first-in first-out (d7 / d0) protocol with both input and output words transferring the most significant bit (msb) first. all inputs are compatible with 5.0 v cmos logic levels. the spi lines perform the following functions: serial clock (sclk) the sclk pin clocks the inter nal shift registers of the 33982B device. the serial input pin (si) accepts data into the input shift register on the falling edge of the sclk signal while the serial output pin (so) shifts data information out of the so line driver on the rising edge of the sclk signal. it is important that the sclk pi n be in a logic low state whenever cs makes any transition. for this reason, it is recommended that the sclk pin be in a logic [0] state whenever the device is not accessed ( cs logic [1] state). sclk has an active internal pulldown, i dwn . when cs is logic [1], signals at the sclk and si pins are ignored and so is tri-stated (high impedance). (see figure 9 and figure 10 .) serial interface (si) this is a serial interface (si) command data input pin. si instruction is read on the falling edge of sclk. an 8-bit stream of serial data is required on the si pin, starting with d7 to d0. the internal registers of the 33982B are configured and controlled using a 4-bit addressing scheme, as shown in table 8 . register addressing and configuration are described in table 9 . the si input has an active internal pulldown, i dwn . serial output (so) the so pin is a tri-stateable ou tput from the shift register. the so pin remains in a high-impedance state until the cs pin is put into a logic [0] state. the so data is capable of reporting the status of the ou tput, the device configuration, and the state of the key inputs. the so pin changes states on the rising edge of sclk and reads out on the falling edge of sclk. fault and input status descriptions are provided in table 15 . chip select (cs ) the cs pin enables communicat ion with the master microcontroller (mcu). when this pin is in a logic [0] state, the device is capable of transferring information to and receiving information from the mcu. the 33982B latches in data from the input shift regist ers to the addressed registers on the rising edge of cs . the device transfers status information from the power output to the shift register on the falling edge of cs . the so output driver is enabled when cs is logic [0]. cs should transition from a logic [1] to a logic [0] state only when sclk is a logic [0]. cs has an active internal pullup, i up . figure 9. single 8-bit word spi communication csb si sclk d7 d1 d2 d3 d4 d5 d6 d0 od7 od6 od1 od2 od3 od4 od5 notes: od0 so 1. rstb is in a logic 1 state during the above operation. 2. d0, d1, d2, ..., and d7 relate to the most recent ordered entry of data into the spss 3. od0, od1, od2, ..., and od7 relate to the first 8 bits of ordered fault and status data out of the device. cs so rst 1. rst is a logic [1] state during the above operation. 2. d7:d0 relate to the most recent ordered entry of data into the device. 3. od7:od0 relate to the first 8 bits of ordered fault and status data out of the device. notes
analog integrated circuit device data freescale semiconductor 21 33982 functional device operation logic commands and registers figure 10. multiple 8-bit word spi communication serial input communication spi communication is accomplished using 8-bit messages. a message is transm itted by the mcu starting with the msb, d7, and ending with the lsb, d0 ( table 8 ). each incoming command message on the si pin can be interpreted using the following bit assignments: the msb (d7) is the watchdog bit and in some cases a register address bit; the next three bits, d6 : d4, are used to select the command register; and the remaining four bits, d3 : d0, are used to configure and control the output and its protection features. multiple messages can be transmitted in succession to accommodate those applications where daisy chaining is desirable or to confirm transmitted data as long as the messages are all multiples of eight bits. any attempt made to latch in a message that is not eight bits will be ignored. the 33982B has defined regist ers, which are used to configure the device and to co ntrol the state of the output. table 9 , summarizes the si registers. the registers are addressed via d6 : d4 of the incoming spi word ( table 8 ). csb si sclk d7 d1* d2* d5* d6* d7* d0 d1 d6 d5 d2 d0* od5 od6 od7 d6 d7 od0 od1 od2 d1 d2 d5 f ig u r e 4 b . m u l t ip l e 8 b it w o r d s p i c o m m u n ic a t io n notes : d0 so 1. r stb is in a logic 1 state during the above operation. 2 . d 0 , d 1 , d 2 , ..., a n d d 7 re la te to th e m o s t re c e n t o rd e re d e n try o f d a ta in to th e s p s s 3. o d 0, o d 1, o d 2, ..., and o d 7 relate to the first 8 bits of ordered fault and status data out of the device. 4. o d 0, o d 1, o d 2, ..., and o d 7 represent the first 8 bits of ordered fault and status data out of the s pss cs sclk si so rst 1. rst is a logic [1] state dur ing the above operation. 2. d7:d0 relate to the most recent ordered entry of data into the device. 4. od7:od0 relate to the first 8 bits of ordered fault and status data out of the device. notes 3. d7*:d0* relate to the previous 8 bits (last command wo rd) of data that was previous ly shifted into the device. table 8. si message bit assignment bit sig si msg bit message bit description msb d7 watchdog in: toggled to satisfy watchdog requirements; also used as a register address bit. d6 : d4 register address bits. d3 : d1 used to configure the inputs, outputs, and the device protection features and so status content. lsb d0 used to configure the inputs, outputs, and the device protection features and so status content.
analog integrated circuit device data 22 freescale semiconductor 33982 functional device operation logic commands and registers device register addressing the following section describes the possible register addresses and their impact on device operation. address x000 ? status register (statr) the statr register is used to read the device status and the various configuration register contents without disrupting the device operation or the regist er contents. the register bits d2, d1, and d0 determine the content of the first eight bits of so data. in addition to the devic e status, this feature provides the ability to read the cont ent of the ocr, sochlr, cdtolr, dicr, osdr, wdr, nar, and uovr registers. (refer to the section entitled serial output communication (device status return data) beginning on page 24 .) address x001 ? output control register (ocr) the ocr register allows the mcu to control the output through the spi. incoming message bit d0 (in_spi) reflects the desired states of the high-side output: a logic [1] enables the output switch and a logic [0] turns it off. a logic [1] on message bit d1 enables the current sense (csns) pin. bits d2 and d3 must be logic [0]. bit d7 is used to feed the watchdog if enabled. address x010 ? select overcurrent high and low register (sochlr) the sochlr register allows the mcu to configure the output overcurrent low and high detection levels, respectively. in addition to protecting the device, this slow blow fuse emulation feature c an be used to optimize the load requirements to match system c haracteristics. bits d2 : d0 are used to set the overcurrent low detection level to one of eight possible levels as defined in table 10 . bit d3 is used to set the overcurrent high detection level to one of two levels as defined in table 11 . address x011 ? current detection time and open load register (cdtolr) the cdtolr register is used by the mcu to determine the amount of time the device will allow an overcurrent low condition before output latches off occurs. bits d1 and d0 allow the mcu to select one of four fault blanking times defined in table 12 . note that these timeouts apply only to the overcurrent low detection levels. if the selected overcurrent high level is reac hed, the device will latch off within 20 s . a logic [1] on bit d2 disables the overcurrent low (cd_dis) detection time-out feature. a lo gic [1] on bit d3 disables the open load (ol) detection feature. address x100 ? direct input control register (dicr) the dicr register is used by the mcu to enable, disable, or configure the direct in pin control of the output. a logic [0] on bit d1 will enable the output fo r direct control by the in pin. a logic [1] on bit d1 will disable the output from direct control. while addressing this register, if the input was enabled for table 9. serial input address and configuration bit map si register serial input data d7 d6 d5 d4 d3 d2 d1 d0 statr x 0 0 0 0 soa2 soa1 soa0 ocr x 0 0 1 0 0 csns en in_spi sochlr x 0 1 0 soch socl2 socl1 socl0 cdtolr x 0 1 1 ol_dis cd_dis oclt1 oclt0 dicr x 1 0 0 fast sr csns high in dis a/o osdr 0 1 0 1 0 osd2 osd1 osd0 wdr 1 1 0 1 0 0 wd1 wd0 nar 0 1 1 0 0 0 0 0 uovr 1 1 1 0 0 0 uv_dis ov_dis test x 1 1 1 freescale internal use (test) x = don?t care. table 10. overcurrent low detection levels socl2 (d2) socl1 (d1) socl0 (d0) overcurrent low detection (amperes) 0 0 0 50 0 0 1 45 0 1 0 40 0 1 1 35 1 0 0 30 1 0 1 25 1 1 0 20 1 1 1 15 table 11. overcurrent high detection levels soch (d3) overcurrent high detection (amperes) 0 150 1 100 table 12. overcurrent low detection blanking time oclt [1:0] timing 00 155 ms 01 10 ms 10 1.2 ms 11 150 s
analog integrated circuit device data freescale semiconductor 23 33982 functional device operation logic commands and registers direct control, a logic [1] for the d0 bit will result in a boolean and of the in pin with its corresponding d0 message bit when addressing the ocr register. similarly, a logic [0] on the d0 pin will result in a boolean or of the in pin with the corresponding message bits when addressing the ocr register. the dicr register is useful if there is a need to independently turn on and off several loads that are pwm?d at the same frequency and duty cycle with only one pwm signal. this type of operation can be accomplished by connecting the pertinent direct in pins of several devices to a pwm output port from the mcu an d configuring each of the outputs to be controlled via their respective direct in pin. the dicr is then used to boolean and the direct in(s) of each of the outputs with the dedicated spi bit that also controls the output. each configured spi bit can now be used to enable and disable the common pwm signal from controlling its assigned output. a logic [1] on bit d2 is used to select the high ratio (c sr1 , 1/40000) on the csns pin. the default value [0] is used to select the low ratio (c sr0 , 1/5400). a logic [1] on bit d3 is used to select the high-speed slew rate. the default value [0] corresponds to the low speed slew rate. address 0101 ? output switching delay register (osdr) the osdr register is used to configure the device with a programmable time delay that is active during output on transitions that are initiated vi a spi (not via direct input). whenever the input is commanded to transition from logic [0] to logic [1], the output will be held off for the time delay configured in the osdr register. the programming of the contents of this register has no effect on device fail-safe mode operation. the default value of the osdr register is 000, equating to no delay, since the switching delay time is 0 ms. th is feature allows the user a way to minimize inrush currents, or surges, thereby allowing loads to be synchronously sw itched on with a single command. table 13 shows the eight selectable output switching delay times, which range from 0 ms to 525 ms. address 1101 ? watchdog register (wdr) the wdr register is used by the mcu to configure the watchdog time-out. watchdog time-out is configured using bits d1 and d0 ( table 14 ). when bits d1 and d0 are programmed for the desired watchdog time-out period, the wd bit (d7) should be toggled as well to ensure that the new time-out period is programm ed at the beginning of a new count sequence. address 0110 ? no action register (nar) the nar register can be used to no-operation fill spi data packets in a daisy chain spi configuration. this allows devices to not be affected by commands being clocked over a daisy-chained spi configurati on, and by toggling the wd bit (d7) the watchdog circuitry will continue to be reset while no programming or data readback functions are being requested from the device. table 13. switching delay osd[2:0] (d2 : d0) turn on delay (ms) 000 0 001 75 010 150 011 225 100 300 101 375 110 450 111 525 table 14. watchdog time-out wd [1:0] (d1: d0) timing (ms) 00 620 01 310 10 2500 11 1250
analog integrated circuit device data 24 freescale semiconductor 33982 functional device operation logic commands and registers address 1110 ? undervoltage / overvoltage register (uovr) the uovr register can be used to disable or enable the overvoltage and/or undervoltage pr otection. by default ([0]), both protections are active. when disabled, an undervoltage or overvoltage condition fault will not be reported in bits d1 and d0 of the output fault register. address x111 ? test the test register is reserved for test and is not accessible with spi during normal operation. serial output communication (device status return data) when the cs pin is pulled low, the ou tput status register is loaded. meanwhile, the data is clocked out msb- (od7-) first as the new message data is clocked into the si pin. the first eight bits of data clocking out of the so, and following a cs transition, are dependant upon the previously written spi word. any bits clocked out of the so pin after the first eight will be representative of the initial message bits clocked into the si pin since the cs pin first transitioned to a logic [0]. this feature is useful for daisy chaining devices as well as message verification. a valid message length is determined following a cs transition of logic [0] to logic [1]. if there is a valid message length, the data is latched into the appropriate registers. a valid message length is a multiple of eight bits. at this time, the so pin is tri-stated and the fault status register is now able to accept new fault status information. the output status register corre ctly reflects the status of the statr-selected regist er data at the time the cs is pulled to a logic [0] during spi communication and / or for the period of time since the last valid spi communication, with the following exceptions: ? the previous spi communication was determined to be invalid. in this case, the status will be reported as though the invalid spi communication never occurred. ? battery transients below 6. 0 v resulting in an under- voltage shutdown of the output s may result in incorrect data loaded into the status register. the so data transmitted to the mcu during the first spi communication following an undervoltage v pwr condition should be ignored. ? the rst pin transition from a logic [0] to logic [1] while the wake pin is at lo gic [0] may result in incorrect data loaded into the status register. the so data transmitted to the mcu during the first spi communication following this condition should be ignored. serial output bit assignment the eight bits of serial output data depend on the previous serial input message, as explained in the following paragraphs. table 15 summarizes the so register content. bit od7 reflects the state of the watchdog bit (d7) addressed during the prior communication. the contents of bits od6 : od0 depend upon the bits d2 : d0 from the most recent statr command soa2 : soa0. previous address soa[2:0] = 000 if the previous three msbs are 000, bits od6 : od0 reflect the current state of the fault register (fltr) ( table 16 ). previous address soa[2:0] = 001 the data in bits od1 and od0 contain csns en and in_spi programmed bits, respectively. table 15. serial output bit map descriptions previous statr d7, d2, d1, d0 serial output returned data soa3 soa2 soa1 soa0 od7 od6 od5 od4 od3 od2 od1 od0 x 0 0 0 wdin otf ochf oclf olf uvf ovf fault x 0 0 1 wdin 0 0 1 0 0 csns en in_spi x 0 1 0 wdin 0 1 0 soch socl2 socl1 socl0 x 0 1 1 wdin 0 1 1 ol_dis cd_dis oclt1 oclt0 x 1 0 0 wdin 1 0 0 fast sr csns high in dis a/o 0 1 0 1 0 1 0 1 fsm_hs osd2 osd1 osd0 1 1 0 1 1 1 0 1 0 wdto wd1 wd0 0 1 1 0 0 1 1 0 0 in pin fsi pin wake pin 1 1 1 0 1 1 1 0 0 0 uv_dis ov_dis x 1 1 1 wdin ? ? ? ? ? ? ? x = don?t care.
analog integrated circuit device data freescale semiconductor 25 33982 functional device operation logic commands and registers previous address soa[2:0] = 010 the data in bit od3 contain the programmed overcurrent high detection level (refer to table 11 ), and the data in bits od2, od1, and od0 contain the programmed overcurrent low detection levels (refer to table 10 ). previous address soa[2:0] = 011 the data returned in bits od1 and od0 are current values for the overcurrent fault blanking time, illustrated in table 12 . bit od2 reports when the overcurrent detection time-out feature is active. od3 reports wh ether the open load circuitry is active. previous address soa[2:0] =100 the returned data contain the programmed values in the dicr. previous address soa[2:0] =101 ? soa3 = 0. the returned data contain the programmed values in the osdr. bit od3 (fsm_hs) reflects the state of the output in the fail -safe mode after a watchdog timeout occurs. ? soa3 = 1. the returned data contain the programmed values in the wdr. bit od2 (wdto) reflects the status of the watchdog circuitry. if wdto bit is logic [1], the watchdog has timed out and the device is in fail-safe mode. if wdto is logic [0], the device is in normal mode (assuming device is powered and not in the sleep mode), with the watchdog either enabled or disabled. previous address soa[2:0] =110 ? soa3 = 0. od2, od1, and od0 return the state of the in, fsi, and wake pins, respectively ( table 17 ). ? soa3 = 1. the returned data contains the programmed values in the uovr register. bit od1 reflects the state of the undervoltage prot ection, while bit od0 reflects the state of the overvoltage protection (refer to table 15 ). previous address soa[2:0] = 111 null data. no previous register read back command received, so bits od2, od1, and od0 are null, or 000. table 16. fault register od7 od6 od5 od4 od3 od2 od1 od0 x otf ochf oclf olf uvf ovf fault od7 (x) = don?t care. od6 (otf) = overtemperature flag. od5 (ochf) = overcurrent high flag. (this fault is latched.) od4 (oclf) = overcurrent low flag. (this fault is latched.) od3 (olf) = open load flag. od2 (uvf) = undervoltage flag. (this fault is latched or not latched.) od1 (ovf) = overvoltage flag. od0 (fault) = this flag reports a fault and is reset by a read operation. note the fs pin reports a fault and is reset by a new switch-on command (via spi or direct input in). table 17. pin register od2 od1 od0 in pin fsi pin wake pin
analog integrated circuit device data 26 freescale semiconductor 33982 typical applications typical applications figure 11. typical applications a/d mcu i/o i/o si so sclk i/o cs so si fs vdd fsi csns rst cs in sclk nc wake nc v pwr 33982B 100nf 10f v dd v dd gnd hs hs vpwr v pwr 2.5f 10nf load rfs 1k 10 k 10 k v dd 10 3 7 8 4 2 9 5 13 1 16 6 15 14 11 voltage regulator v dd v pwr nc 12 10k 10k 10k 10k 10k
analog integrated circuit device data freescale semiconductor 27 33982 packaging soldering information packaging soldering information soldering information the 33982B is packaged in a surface mount power package intended to be soldered directly on the printed circuit board. the 33982B was qualified in accordance with jedec standards jesd22-a113-b and j-std-020a. the recommended reflow conditions are as follows: ? convection: 225c +5 .0/ -0c ? vapor phase reflow (vpr): 215c to 219c ? infrared (ir) / convection: 225c +5.0 / -0c the maximum peak temperat ure during the soldering process should not exceed 230c. the time at maximum temperature should range from 10 s to 40 s maximum.
analog integrated circuit device data 28 freescale semiconductor 33982 packaging package dimensions package dimensions for the most current revision of the package, visit www.freescale.com and perform a keyword search on 98arl10596d. pna suffix 16-pin pqfn nonleaded package 98arl10521d issue c
analog integrated circuit device data freescale semiconductor 29 33982 packaging package dimensions package dimensions (continued) pna suffix 16-pin pqfn nonleaded package 98arl10521d issue c
analog integrated circuit device data 30 freescale semiconductor 33982 additional documentation thermal addendum (rev 3.0) additional documentation thermal addendum (rev 3.0) introduction this thermal addendum is provided as a supplement to the mc33982B technical datasheet. the addendum prov ides thermal performance information that may be critical in the design and devel opment of system a pplications. all electrical, application, and packaging in formation is provided in the datasheet. packaging and thermal considerations this package is a dual die package. there are two heat sources in the package independently heating with p 1 and p 2 . this results in two junction temperatures, t j1 and t j2 , and a thermal resistance matrix with r ja mn . for m , n = 1, r ja11 is the thermal resistance fr om junction 1 to the reference temperature while only heat so urce 1 is heating with p 1 . for m = 1, n = 2, r ja12 is the thermal resistance from junction 1 to the reference temperature while heat source 2 is heating with p 2 . this applies to r j21 and r j22 , respectively. the stated values are solely for a thermal performance comparison of one package to another in a standardized environment. this metho dology is not meant to and will not predict the performance of a package in an application-specific environm ent. stated values were obtained by m easurement and simulation according to the standards listed below. standards figure 12. surface mount for power pqfn with exposed pads high-side switch 33982 pna suffix 98arl10521d 16-pin pqfn 12 mm x 12 mm note for package dimensions, refer to the 33982B data sheet. t j1 t j2 = r ja11 r ja21 r ja12 r ja22 . p 1 p 2 table 18. thermal pe rformance comparison thermal resistance 1 = power chip, 2 = logic chip [ c/w] m = 1, n = 1 m = 1, n = 2 m = 2, n = 1 m = 2, n = 2 r ja mn (1) , (2) 20 16 39 r jb mn (2) , (3) 62.026 r ja mn (1) , (4) 53 40 73 r jc mn (5) <0.5 0.0 1.0 notes: 1. per jedec jesd51-2 at natural convection, still air condition. 2. 2s2p thermal test board per jedec jesd51-7and jesd51-5. 3. per jedec jesd51-8, with the board temperature on the center trace near the power outputs. 4. single layer thermal test board per jedec jesd51-3 and jesd51-5. 5. thermal resistance betw een the die junction and the exposed pad, ?infinite? heat sink attached to exposed pad. note: recommended via diameter is 0.5 mm. pth (plated through hole) via must be plugged / filled with epoxy or solder mask in order to minimize void formation and to avoid any solder wicking into the via. 1.0 1.0 0.2 0.2 * all measurements are in millimeters
analog integrated circuit device data freescale semiconductor 31 33982 additional documentation thermal addendum (rev 3.0) figure 13. thermal test board device on thermal test board r ja is the thermal resistance between die junction and ambient air. this device is a dual die package. index m indicates the die that is heated. index n refers to the number of the die where the junction temperature is sensed. hs hs 16 15 vpwr 14 gnd 13 csns in fs fsi cs sclk rst wake si vdd so nc 1 11 10 9 8 7 6 5 4 3 2 12 16-pin pqfn 0.90 mm pitch 12.0 mm x 12.0 mm body 33982B pin connections transparent top view a a material: single layer printed circuit board fr4, 1.6 mm thickness cu traces, 0.07 mm thickness outline: 80 mm x 100 mm board area, including edge connector for thermal testing area a: cu heat-spreading areas on board surface ambient conditions: natural convection, still air table 19. thermal resistance performance thermal resistance area a (mm 2 ) 1 = power chip, 2 = logic chip ( c/w) m = 1, n = 1 m = 1, n = 2 m = 2, n = 1 m = 2, n = 2 r ja mn 055 42 74 300 41 32 66 600 39 29 65
analog integrated circuit device data 32 freescale semiconductor 33982 additional documentation thermal addendum (rev 3.0) figure 14. device on thermal test board r ja figure 15. transient thermal resistance r ja (1.0 w step response) device on thermal test board area a = 600 (mm 2 ) 0 10 20 30 40 50 60 70 80 heat spreading area a [mm2] thermal resistance [oc/w] 0 300 600 r ja11 r ja22 r ja12 =r ja21 x 0.1 1 10 100 1.00e-03 1.00e-02 1.00e-01 1.00e+00 1.00e+01 1.00e+02 1.00e+03 1.00e+04 time(s) thermal resistance (cw) r ja11 r ja22 r ja12 =r ja21 x
analog integrated circuit device data freescale semiconductor 33 33982 revision history revision history revision date description of changes 10.0 2/2006 ? implemented revision history page ? deletion of mc33982 part number, replaced with mc33982B. 11.0 5/2006 ? corrected pin connections to the proper case outline ? added final sentence to open load fault (non-latching) ? corrected heading labels on input timing switching characteristics ? changed labels in the typical applications drawing ? corrected package dimensions to revision c ? added thermal addendum (rev 3.0) . 12.0 1/2007 ? added rohs logo to the data sheet
mc33982 rev. 12.0 1/2007 information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2007. all rights reserved. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com

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